AMD has licensed a memory chip technology that could allow it to increase its processors' cache sizes fivefold without changing the size of each chip's die.

The technology is called Z-RAM and was developed by US-Swiss start-up Innovative Silicon, EETimes reports (http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=V2AQAAYC3GVIQQSNDBESKHA?articleID=177101749). IS' technique strips out the capacitor components commonly integrated into on-chip memory. The upshot: more space is created for memory cells, boosting the size of the cache.

IS claims Z-RAM can deliver up to five times the storage density of embedded S-RAM, the kind of memory from which most on-chip caches are constructed. It also developed Z-RAM to be fabbed using silicon-on-insulator (SOI) technology, which AMD already uses to produce its processors, as does IBM and Freescale.

AMD's corporate VP of technology development, Craig Sander, said IS' initial data "looks very promising". But he warned that much more work has to be done to see how well the technology can be integrated into AMD's CPUs and how well it scales as AMD moves to future fabrication nodes, such as 45nm. AMD will be testing Z-RAM at 90nm and 65nm, but the technology's introduction into shipping product could come much later. ®

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